High-bandwidth memory becomes the choke point for AI accelerators as AMD plans Seoul meetings with Samsung and Naver, while supply forecasts, HBM4 roadmaps and packaging capacity reshape pricing power, data centre buildouts and investor focus.

SINGAPORE, SG / ACCESS Newswire / March 18, 2026 / Merifund Capital Management is flagging a tightening race for high-bandwidth memory, with AMD's chief executive set for talks in South Korea next week that put component supply on the same agenda as AI performance. Anthony Saunders, Director of Private Equity at Merifund Capital Management Pte. Ltd., describes the moment as "the point where the memory stack dictates the pace of the AI build, not the other way around".

Lisa Su's itinerary includes a planned meeting with Samsung Electronics Chairman Jay Y. Lee on the 18th to map cooperation across HBM, DRAM and NAND procurement. It is Su's first business trip to the country since taking the top job more than a decade ago, a signal of how procurement and partnership building now sit at the core of accelerator strategy.

Samsung is moving the latest HBM generation into mass production this month and industry expectations still point to tight availability through the coming year as hyperscalers and national AI programmes scale capacity. Saunders calls the current market "a negotiation for time as much as silicon", where qualification status and delivery windows increasingly decide whose accelerators reach volume first. Samsung declines to comment publicly on the meeting schedule, reflecting how sensitive memory allocations remain when multiple platform launches compete for the same supply.

The visit also includes Naver Chief Executive Officer Choi Soo-yeon, with Naver Cloud acknowledging the planned discussion while keeping the agenda private. Industry watchers expect a focus on data centre expansion, sovereign AI infrastructure and next-generation computing partnerships, with Naver's scale positioning it as a consequential buyer of accelerators in the region.

The strategic importance of HBM is rooted in physics and packaging. Current HBM stacks use 1,024-bit interfaces and the HBM4 specification doubles that width to 2,048 bits, pushing bandwidth targets up to 4 TB/s per stack in near-term designs. In shipping flagship accelerator configurations, memory capacity can reach 640 GB per unit, turning each additional stack into a direct lever on training throughput and inference efficiency.

TrendForce estimates HBM demand rises 130% over the most recently completed year, and market projections continue to point to a further 70% expansion across the coming four quarters as new accelerators widen memory footprints.

That demand is reshaping the broader memory complex. Manufacturers are rebalancing fabrication capacity towards HBM, with industry estimates putting the bit allocation at roughly four-to-one compared with DDR5 in current planning, tightening availability for standard DRAM categories even as pricing holds firmer. NAND suppliers benefit from data centre adoption of high-capacity solid state drives, with 30 TB and 60 TB QLC configurations appearing more often in current deployments.

Supplier competition is intensifying at the top end. SK Hynix clears a key HBM4 validation milestone in the third quarter of the previous calendar year and is widely expected to hold roughly two-thirds of initial allocations for Nvidia's next platform cycle, while Samsung secures Nvidia quality certification last month and reports 11 gigabits per second transmission rates in recent testing. Merifund Capital Management tracks this as a pricing power shift, with memory roadmaps increasingly synchronised to packaging capacity and customer-specific tuning. Saunders characterises the compressed qualification loop as "an arms race measured in quarters, not years".

The partnership scope stretches beyond memory. Samsung Electro-Mechanics supplies larger-format substrates from facilities in Busan and Vietnam to support chiplet integration, and Samsung and AMD are progressing network products into commercial deployments, including virtualised RAN and private network solutions, with rollouts such as Videotron's core gateway deployment built on AMD EPYC 9005 Series CPUs.

The timetable is set to intersect with Nvidia's GTC conference in San Jose, running from the 16th through the 19th and billed to draw more than 30,000 attendees from roughly 190 countries across the four-day programme. The opening-day keynote is scheduled for 11 a.m. local time, with a separate quantum track following on the 20th.

For investors, the signal is clear: memory supply is no longer a background variable in the AI hardware cycle. Merifund Capital Management is focusing on HBM availability, qualification velocity and packaging constraints as the factors most likely to separate winners from laggards in the next wave of accelerator shipments, and Saunders sums up the checklist as "secure the stacks, qualify them fast, and ship at scale".

About Merifund Capital Management

Founded in 2010, Merifund Capital Management Pte. Ltd. (UEN: 201024554E) is a Singapore-headquartered hedge fund management firm serving accredited investors, family offices, foundations and endowments. Its strategies span traditional long-only mandates, long/short equity, global macro, event-driven and systematic approaches. The firm uses derivatives to optimise market opportunities while maintaining a consistent focus on capital preservation, liquidity and prudent risk management, and integrates ESG considerations as part of its sustainability standards. Merifund is expanding its offering with the aim of making selected strategies accessible to retail investors. Insights are available at https://merifund.com/insights. For media enquiries or additional information, contact Tao Yang at media@merifund.com or visit https://merifund.com.

SOURCE: Merifund Capital Management Pte. Ltd.